1. Field of the Invention
The invention relates to a flash memory device and a method of fabricating the same, and, more particularly, to a flash memory device and a method of fabricating the same, which can prevent the occurrence of a bridge between contact plugs and improve a gap-fill characteristic of the contact plugs.
2. Brief Description of Related Technology
In recent years, active research has been performed to increase the integration and improve the performance of semiconductor memory devices. Problems resulting from the increased integration of semiconductor memory devices are described in detail with reference to NAND flash memory devices, as an example only. NAND flash memory devices advantageously have increased integration and a low manufacturing unit cost.
A NAND flash memory device consists of a plurality of cell strings. Each cell string includes a source select transistor, a plurality of memory cells, and a drain select transistor, which are connected in series. The source of the source select transistor is coupled to a common source line, and the drain of the drain select transistor is coupled to a bit line. Gates of the source select transistors are connected to form a source select line, gates of the drain select transistors are connected to form a drain select line, and gates of the memory cells are connected to form a word line.
A gate pattern, including the word line, the source select line, and the drain select line, has a structure in which a tunnel dielectric layer, a floating gate, a dielectric layer, and a control gate are sequentially stacked. A contact hole, which exposes the floating gate, is formed in the dielectric layer of the drain select line and the source select line. The floating gate is electrically connected to the control gate through the contact hole.
A lower structure of the flash memory device including the gate pattern is covered with an insulating layer to isolate it from an upper structure, which includes the common source line and the bit line. The lower structure is electrically connected to the upper structure by a contact plug formed within a contact hole formed in the insulating layer.
As a result of the increased integration of memory devices and the miniaturization of cell size, the critical dimension (CD) of a contact hole has decreased, and the process margin for forming the contact hole has become insufficient. A drain contact plug of a flash device is conventionally formed by forming a plurality of string structures, each including a source select transistor, a plurality of memory cells, and a drain select transistor in a semiconductor substrate. A source contact plug is formed, a pre-metal dielectric layer is formed over the source contact plug, and a contact hole that exposes the drain of the drain select transistor is formed. Next, tungsten (W) is deposited on the pre-metal dielectric layer including the contact hole and then polished, thereby forming a drain contact plug to gap-fill the contact hole.
A bowing phenomenon, in which a width of an intermediate depth of the contact hole is widened, can occur during formation of the drain contact hole when a bottom CD of the drain contact hole is secured to a certain level. The bowing phenomenon is a result of the pre-metal dielectric layer etched to form the drain contact being too thick. However, in a conventional method, this thickness is needed to secure the bottom CD of the drain contact hole. At the time of a subsequent wet cleaning process, the contact holes are connected where the bowing has occurred, which causes contact plugs formed within the contact holes to be connected, resulting in formation of a bridge.
Conventional methods of forming the contact holes to prevent an inter-hole bridge disadvantageously result in contact holes that are too small, and an increased aspect ratio. Accordingly, gap-fill failure of the contact plug, such as a void, is generated, causing an electrical short.
An inter-hole bridge can also result after gap-filling the contact hole with a pre-metal dielectric layer, during a wet cleaning process for removing micro defect materials formed during deposition of the pre-metal dielectric layer. This problem does not lie in a bridge occurring over the holes and is not detected upon in-line testing, making it difficult to detect this problem.